1. Field of the Invention
The present invention relates to a step-up method and a semiconductor integrated step-up circuit.
2. Description of the Prior Art
FIG. 1 shows a triple step-up circuit according to a prior art.
The circuit has an n-channel MOS (NMOS) transistor 101, p-channel MOS (PMOS) transistors 102 to 106, and capacitors 107 to 109. The NMOS transistor 101 is controlled by a signal A2, and the PMOS transistor 102 is controlled by a signal /A2, i.e., an inversion of the signal A2. The PMOS transistors 103 and 104 are controlled by a signal /B2, and the PMOS transistors 105 and 106 are controlled by a signal /C2.
FIG. 2 is a timing chart showing the operation of the triple step-up circuit of FIG. 1.
In a period T1, the signal A2 is HIGH and the signal /A2 is LOW, to turn ON the NMOS transistor 101 and PMOS transistor 102. At this time, the signals /B2 and /C2 are each HIGH to turn OFF the PMOS transistors 103 to 106. As a result, a ground voltage GND is applied to a terminal "a" of the capacitor 107 through the NMOS transistor 101, and an input voltage V2in is applied to the other terminal "b" thereof through the PMOS transistor 102.
When the signal A2 changes to LOW and the signal /A2 to HIGH to turn OFF the NMOS transistor 101 and PMOS transistor 102, the capacitor 107 holds a potential difference corresponding to the input voltage V2in.
In a period T2, the signal /B2 changes to LOW to turn ON the PMOS transistors 103 and 104. At this time, the signal /C2 is still HIGH to turn OFF the PMOS transistors 105 and 106. As a result, the input voltage V2in is applied to the terminal a of the capacitor 107 through the PMOS transistor 108. Then, the capacitor 107 causes coupling, to increase the voltage of the terminal b thereof twice as large as the input voltage V2in, and the capacitor 108 is charged through the PMOS transistor 104.
When the signal/B2 changes to HIGH to turn OFF the PMOS transistors 103 and 104, the voltage of a terminal "c" of the capacitor 108 becomes twice as large as the input voltage V2in.
In period T3, the signal A2 changes to HIGH to turn ON the NMOS transistor 101 and PMOS transistor 102. Thereafter, the signal A2 changes to LOW to turn OFF the NMOS transistor 101 and PMOS transistor 102, and the capacitor 107 holds a potential difference corresponding to the voltage V2in.
In period T4, the signal /C2 changes to LOW to turn ON the PMOS transistors 105 and 106. Then, the voltage of the terminal c of the capacitor 108, which is twice as large as the voltage V2in, is applied to the terminal a of the capacitor 107 through the PMOS transistor 105. As a result, the capacitor 107 causes coupling to make the voltage of the terminal b of the capacitor 107 three times as large as the voltage V2in, and the capacitor 109 is charged through the PMOS transistor 106.
When the signal /C2 changes to HIGH to turn OFF the PMOS transistors 105 and 106, the voltage of a terminal "d" of the capacitor 109 will be three times as large as the voltage V2in. Namely, an output voltage V2out is three times as large as the input voltage V2in.
The problems of this step-up circuit will be explained.
The output voltage V2out becomes three times as large as the input voltage V2in through the operations of (1) charging the capacitor 107, (2) doubling the input voltage V2in by coupling, (3) charging the capacitor 107, and (4) multiplying the input voltage V2in by three by coupling. Each step-up cycle must involve these four operations corresponding to the periods T1 to T4 of FIG. 2.
To provide an output voltage that is "m" times larger than an input voltage (m being an integer equal to or larger than two), the prior art needs "2.times.(m-1)" operations. Namely, the prior art takes a long time to provide a stepped-up voltage. When supplying the output voltage V2out to the next circuit, such a long step-up time causes a large drop in the output voltage with respect to a load current.
The step-up efficiency of the capacitors 107 to 109 of the prior art during an initial stage will be explained. It is supposed that the MOS transistors have no ON-resistance and the capacitors have an identical capacitance value.
Each of the capacitors is discharged in the initial stage, to have no potential difference between the opposite electrodes thereof. In the period T1, the terminal b of the capacitor 107 holds the input voltage V2in. In the period T2, the capacitors 107 and 108 share charges. Namely, the terminal c of the capacitor 108 holds a voltage of V2in=(2.times.V2in [the voltage of the terminal b of the capacitor 107]+0 [the voltage of the terminal c of the capacitor 108 before sharing charges])/2 [the number of capacitors]. This voltage V2in provided by the capacitor 108 in the initial stage is 50% of the voltage "2.times.V2in" provided by the same under a steady state.
In the period T3, the terminal b of the capacitor 107 holds the voltage V2in. In the period T4, the capacitors 107 and 109 share charges. Accordingly, the output voltage V2out will be V2in=(2.times.V2in [the voltage of the terminal b of the capacitor 107]+0 [the voltage of the terminal d of the capacitor 109 before sharing charges])/2 [the number of capacitors]. This output voltage V2out in the initial stage is 33% of the output voltage "3.times.V2in" expected under a steady state.
Namely, when providing an output voltage n times larger than an input voltage, the prior art provides only "1/n.times.100" percents of the expected output voltage during an initial stage.